Three dimensionals interconnection method and electronic device obtained by same

ABSTRACT

The invention relates to a method of interconnection in three dimensions and to an electronic device obtained by this process.  
     To increase the compactness of integrated circuit modules, the method consists in stacking and adhesively bonding ( 100 ) packages containing a chip connected to the output leads via connection conductors inside each package, in cutting ( 101 ) through the packages near the chips in order to form a block, the conductors being flush with the faces of the block, and in making ( 102 ) the connections on the faces of the block by metalizing ( 1021 ) and then etching ( 1022 ) the outlines of the connections.  
     The method also applies to the matching of packages in the replacement of obsolete circuits.

[0001] The invention relates to a method of interconnection in threedimensions for packages containing at least one electronic component. Italso relates to an electronic device obtained by this method.

[0002] The production of current electronic systems, whether civil ormilitary, must take into account the requirements of ever increasingcompactness, because of the ever increasing number of circuits involved.

[0003] In this search for greater compactness, it has already beenproposed to produce stacks of integrated circuit chips or, as describedin French patent FR 2 688 630, chip-encapsulating packages, theinterconnection being accomplished in three dimensions using the facesof the stack as interconnection surfaces for making the necessaryconnections between output leads.

[0004] The encapsulation of chips in plastic packages, such as forexample the standard packages of SOJ (Small Outline J-lead), TSOP (ThinSmall Outline Package) or CSP (Chip Scale Package) type has manyadvantages. Firstly, these packages have been tested and burned-in bythe manufacturer, although these operations are very difficult to carryout on bare chips. Moreover, it is generally difficult to obtain barechips from manufacturers. The combination of these reasons thereforemakes it preferential to use packages, which are appreciably lessexpensive and easier.

[0005] The stacking of packages according to the solution of theabovementioned patent involves the following main operations:straightening the output leads in order to facilitate alignment andmolding; stacking of the plastic packages; encapsulation with resin andcuring; cutting of the block; metalization; etching of the outlines ofthe connections on the faces of the block. Moreover, since the cuttingis carried out on the outside of the packages in order to use the outputleads of the packages for the interconnection in three dimensions, the3D module obtained always has, in the plane of the packages, dimensionsgreater than the original packages.

[0006] The object of the invention is, on the one hand, to simplify theoperations of manufacturing a 3D module and, on the other hand, toappreciably reduce the volume occupied. It is based on the idea ofcutting the block not any longer on the outside of the packages, butthrough these packages.

[0007] According to the most general aspect of the invention, what istherefore provided is a method of interconnection in three dimensionsfor at least one package containing at least one electronic componentand furnished with connection conductors for connecting, inside saidpackage, connection pads on the component to output leads toward theoutside of the package, said method being characterized in that itcomprises the following steps:

[0008] a) stacking and assembling the elements to be interconnected;

[0009] b) cutting through the package or packages, near said components,in order to form a block leaving the cross section of the connectionconductors flush;

[0010] c) production of the electrical connections between theconductors of the various elements on the faces of said block.

[0011] More particularly, for interconnecting several packages together,provision is made for said stacking and assembling step a) to consist instacking and adhesively bonding the packages.

[0012] This method thus dispenses with the operations of straighteningthe output leads and of encapsulation and curing, the latter beingreplaced by a simple adhesive bonding operation. The method has thusbeen simplified.

[0013] Moreover, the cutting of the block is carried out near the chips,and therefore through the packages, and no longer on the outside of thepackages, hence a reduction of almost 50% in the area of the block in aplane parallel to the packages.

[0014] To achieve this solution to the problems of reducing the volumeof the electronic devices, it is clear that it was necessary, on the onehand, to go counter to the idea that a package is needed for variousfunctions, namely protection against the external environment, handlingnot hazardous to the chip and electrical connection to the outside, andmust not be cut, and that it was necessary, on the other hand, to statethat the transfer molding resins used on the inside of the packages bythe semiconductor industry were substantially of the same compositionand filler content as the encapsulation resins used in the prior art.

[0015] Another, particularly beneficial, application relates to thereplacement of complex components rendered obsolete, that is to say nolonger available on the market, when, for example, a new series of anold piece of equipment has to be manufactured. During the originaldesign of the equipment, ASIC circuits were able in particular to bedefined, which were produced by a supplier who, since then, has changedtechnology. Hitherto, it was necessary to redevelop a new ASIC. However,there are programmable integrated circuits with a sea of ports, of theFPGA (Field Programmable Gate Array) which would make it possible toprogram the same functions as the original ASIC circuit. The drawback isthat the arrangement, the number of outputs and the dimensions of theASIC circuit are different from those of the FPGA circuits available: ingeneral, the FPGA circuits, with very large-scale integration, have asubstantially larger number of outputs than the ASIC circuit that itwould be desired to replace. To produce the functions of an ASIC with 44outputs for example, only this number of outputs of an FPGA circuit (forexample with 144 outputs) would be used. In addition, the arrangement ofthese outputs will not be the same, hence a mismatch with respect to thecard on which this circuit has to be mounted. Finally, there is a riskof the footprint of the FPGA circuit being different and, in general,larger.

[0016] The invention makes it possible, through its principle, to solvethese problems. According to this new application, provision is made toassociate with a complex circuit contained in a package a matchingcircuit consisting of a printed circuit, of a first array of selectionconductors, allowing it to be connected to the suitable outputs of thepackage, and of a second, matching array, the leads of which reproduce,in terms of number and arrangement, the desired pattern, the printedcircuit providing the interconnection between the two arrays.

[0017] By implementing the invention, it is thus possible to produce anelectronic circuit with interconnection in three dimensions, of smallfootprint, suitable for the desired application.

[0018] This other aspect of the invention therefore provides a method,as generally defined above, for interconnecting a package with a circuitfor matching the array of the output leads, characterized in that saidstacking and assembly step a) consists in stacking and assembling saidmatching circuit against said package by adhesive bonding orencapsulation.

[0019] The invention will be more clearly understood and furtherfeatures and advantages will become apparent from the description belowand from the appended drawings in which:

[0020]FIG. 1 is a view of the inside and from above of a package showingthe connections of a chip to the output leads;

[0021]FIG. 2 is a sectional view of the package of FIG. 1 in the planeB;

[0022]FIG. 3 shows the block diagram of the method according to theinvention;

[0023]FIG. 4 is a sectional view of how the packages are assembledduring one step of the method according to the invention;

[0024]FIG. 5 is a partial perspective view of the 3D module obtained;

[0025]FIG. 6 illustrates an initial step of an application variant ofthe invention;

[0026]FIGS. 7 and 8 show sectional views during successful steps of thevariant of FIG. 6;

[0027]FIG. 9 is a side view of the module obtained; and

[0028]FIG. 10 is the block diagram of the method according to thisvariant of the invention.

[0029]FIG. 1 shows, by way of example and in a simplified manner, theinside of a TSOP package seen from above. A chip 1 (for example a memorychip) has connection pads 10 aligned in two rows. These pads areconnected to an array 4 of output leads 40 via a set 3 of connectingconductors 30. The link between the pads 10 and the conductors 30 ismade by connecting up the wires 11. The assembly is enclosed in aplastic package 2.

[0030]FIG. 2 shows the package 2 in section in the plane B. Theconductors 30 terminate in bent-over output leads 40.

[0031] The method according to the invention, applied to the mutualinterconnection in three dimensions of packages, is illustrated by theblock diagram of FIG. 3. In a first step 100, the packages are stackedand assembled by adhesive bonding as shown in FIG. 4, in which thereference 5 denotes films of adhesive between the packages.

[0032] In a second step 101, the assembly is cut, not at the outputleads in the plane A for example (FIG. 1), as in the prior art, butthrough the packages 2, in the plane of cutting A′ (or B′) near the chip1 so as to cut the connection conductors 30, the section 31 of which isflush with the faces of the block obtained.

[0033] As may be seen, the planes of sections such as A′ or B′ are muchcloser to the chip 1, hence a considerably reduced footprint. Forexample, the sawing may be carried out at a distance of between 0.5 and2 mm around the chip, depending on the chip wire-bonding techniques usedby the semiconductor manufacturer.

[0034] Step 102 then consists in making the connections between theconductors of the various packages to the faces of the block obtained.Various techniques can be used to do this. Preferably, in a first stage1021, the faces of the block are metalized and, in a second stage 1022,the outline of the connections are etched, for example by laser etching.The block 6 obtained is shown in FIG. 5. It may be seen that the section31 of the connection conductors of the packages 2 are connected byconnections 71 on the faces of the block 6, which may terminate inconnection pads 72 toward the outside or to the sections 77 of theoutput arrays 78 of the block. This step of the process is described indetail in, for example, the aforementioned patent FR 2 688 630.

[0035] As may be seen, the method according to the invention allows themanufacture of the 3D modules to be simplified by eliminating theoperation of straightening the output leads or tabs, since they areremoved during the cutting, and by replacing the encapsulation andcuring step with a single adhesive bonding operation.

[0036] Another application of the invention will now be described withinthe context of the replacement of a specific circuit of the ASIC typewith a circuit of general application of the FPGA type, which may beprogrammed in order to fulfil the functions of the original ASICcircuit. As already explained, such a programming operation means ingeneral that only some of the ports and outputs of the FPGA circuit areused and the arrangement of the outputs has to be redistributed in orderto be matched to the application envisioned.

[0037] To do this, knowing the number of outputs to be used and theirdistribution, a matching circuit CA (FIG. 6) is produced, whichcomprises a first selection array 52 placed on one face and on the edgesof a printed circuit 50 facing the package 20 of the FPGA circuit. Thispackage contains at least one chip 12 whose connection pads (not shown)are connected to the leads 42 of an output array via conductors 41. Theleads 52 of the selection array are positioned so as to correspond tothe conductors 41 used, in what will be the plane of cutting C.Moreover, the opposite face of the printed circuit 50 carries, along itsedges, a matching array of output leads 53, the positioning of which isthat of the leads of the ASIC circuit that it is wished to replace. Theinterconnection between the two arrays is effected by means of thetracks of the printed circuit 50. The leads 52 are soldered to thesetracks by the soldered joints 54 and the leads 53 by the soldered joints55. For assembling the package and the matching circuit CA, an arraysupport 60 is provided, the end 56 of the leads of the array 53 engagingin the slots of the array support.

[0038] In a first step 100′ (FIG. 10), the package 20 and the matchingcircuit CA are assembled so that the plane of cutting C is near the chip12 and cuts off the ends of the arrays 52 and 53. The assemblingoperation is performed, for example, using beads of adhesive placed onboth faces of the printed circuit 50. The total amount of adhesive mustbe sufficient to fill the volumes lying between the printed circuit 50and the package 20 and the array support 60, respectively, and so thatan excess flows out at 70 during assembling, so as to allow the sawingthrough the core of the adhesive (with neither an empty space norholes). Under the pressure used to assembly the package 20 to thesupport 60, as has just been mentioned, the adhesive flows out in orderto coat the ends of the leads 52 and 53, as shown at 70 in FIG. 7. Theassembling operation may also be performed by encapsulation betweenpackage and support 60 with a curable resin, such as an epoxy resin.

[0039] The next step 101′ consists, as previously, in cutting throughthe package through the plane C.

[0040] A block M is thus obtained, seen in partial section in FIG. 8, inwhich the conductors 41 and the leads of the arrays 52 and 53 are flushwith the face of the block. This FIG. 8 furthermore shows that the end56 of the leads of the matching array have been suitably bent over.

[0041] Step 102′ (FIG. 10) then consists in making, on the faces of theblock M, the desired connections in three dimensions between theconductors 41 of the package and the leads of the first selection array52, using any conventional technology.

[0042] For example, the faces of the block are metalized (1021′) andthen the outlines of the connections are etched (1022′) for example bylaser etching.

[0043]FIG. 9 shows, seen from the side, the module M obtained. On theface shown may be seen the sections of the conductors 41, of theselection array 52 and of the matching array 53. The metalization 80covers all the faces of the block M. Laser etching 81 is used to etchthe outline of the connections between conductors 41 and leads of thearray 52 and to isolate the leads of the matching array 53. For example,a used output 410 of the package is connected via the connection 73 tothe lead 520. In contrast, outputs such as 411 are not used.

[0044] Of course, the illustrative examples described in no way limitthe invention; in particular, techniques other than completemetalization of the block could be used to make the connections in 3D,or etching methods other than laser etching could be used. Provisioncould also be made not to extend the leads 53 beyond the edge of theprinted circuit, which would avoid having to make them flush andtherefore having to isolate them by etching. However, since theinterconnection between the output array 56 and the electronic circuit12 is achieved by soldering the array to the printed circuit 50, forapplications requiring high reliability in a harsh environment, it isundesirable for there to be a risk of the solder (tin/lead, whosemelting point is in general 180° C.) reflowing when the assembly isitself soldered to a printed circuit card having all the othercomponents. The interconnection via the metalized face of the blocktherefore makes this connection of the array 56 secure. However, formany noncritical applications, the fact of simply soldering the array tothe printed circuit 50 constitutes a real simplification.

1. A method of interconnection in three dimensions for at least onepackage (2; 20) containing at least one electronic component (1; 12) andfurnished with connection conductors (30; 41) for connecting, insidesaid package, connection pads (10) on the component to output leads (40;42) toward the outside of the package, said method being characterizedin that it comprises the following steps: a) stacking and assembling(100; 100′) the elements to be interconnected; b) cutting (101; 101′)through the package or packages, near said components, in order to forma block (6; M) leaving the cross section of the connection conductorsflush; c) production (102; 102′) of the electrical connections betweenthe conductors of the various elements on the faces of said block. 2.The method as claimed in claim 1, for interconnecting several packagestogether, characterized in that said stacking and assembling step a)consists in stacking and adhesively bonding (101) the packages (2). 3.The method as claimed in claim 2, characterized in that, since saidcomponent is an electronic chip, said cutting step b) is carried out ata distance of between about 0.5 and 2 mm from the chips.
 4. The methodas claimed in claim 1, for interconnecting a package (20) with a circuit(CA) for matching the array of the output leads (56), characterized inthat said stacking and assembly step a) consists in stacking andassembling (101′) said matching circuit (CA) against said package (20)by adhesive bonding or encapsulation.
 5. The method as claimed in claim4, characterized in that, since the component is an electronic chip,said cutting step b) is carried out at a distance of between 0.5 and 2mm from the chip.
 6. The method as claimed in either of claims 4 and 5,characterized in that, since said matching circuit consists of a printedcircuit (50) along the edges of which, on a face which faces thepackage, a first array (52) for selecting the output leads (42) of thepackage to be connected and, on the other face, a second, matching array(53, 56) are placed, said matching circuit (CA) is assembled with thepackage (20) so that the plane of cutting (C) cuts off the ends of thearrays (52, 53) of said circuit.
 7. The method as claimed in any one ofclaims 1 to 6, characterized in that step c) of making the electricalconnections consists in: c.1) metalizing (1021; 1021′) the faces of saidblock; c.2) etching (1022; 1022′) the outlines of said connections (71;72; 73; 77).
 8. The method as claimed in claim 7, characterized in thatstep c.2) of etching the outlines of the connections is carried out bylaser etching.
 9. An electronic device with interconnection in threedimensions, comprising packages (2) which contain at least oneelectronic component (1) and are furnished with connection conductors(30) inside said packages, in which device said packages are stacked andadhesively bonded, characterized in that it is formed by a block (6) cutthrough the packages (2) near the components (1) so that said connectionconductors (30) are flush with the faces of the block and in that thefaces of the block bear connections (71, 72) connecting said connectionconductors.
 10. An electronic device with interconnection in threedimensions, comprising a package (20) which contains at least oneelectronic component (1) and is furnished with connection conductors(41) inside the package, characterized in that it furthermore includes amatching circuit (CA) with which said package is assembled andconsisting of a printed circuit (50), of a first, selection array (52)and of a second, matching array (53, 56), these arrays being placedalong the edges of the printed circuit, on the two faces of the latterrespectively, the face carrying the first array facing the package andthe package/matching circuit assembly having been cut through thepackage and the ends of the arrays in order to form a block (M) in whichthe section of the connection conductors (41) and of the arrays (52, 53)is flush with the faces of the block, and in that the faces of the blockcarry connections (73) connecting said connection conductors (41) tosaid first selection array (52).
 11. The electronic device as claimed inclaim 10, characterized in that the faces of the block (M) are metalized(80) and etched (81) so as to define the outlines of said connections(73) and to isolate the sections of the second array (53).